Thin film semiconductor device and organic light-emitting display device

ABSTRACT

A thin film semiconductor device including a thin film transistor (TFT) that maintains a constant electrical characteristic and an organic light-emitting display device. The thin film semiconductor device includes: a substrate; and a thin film transistor (TFT) disposed on the substrate and comprising a semiconductor layer comprising a source region and a drain region, wherein a part of the source region is spaced apart from the drain region and partially surrounds the drain region, and wherein a part of the drain region is spaced apart from the source region and partially surrounds the source region.

CLAIM OF PRIORITY

This application makes reference to, incorporates the same herein, andclaims all benefits accruing under 35 U.S.C. §119 from an applicationearlier filed in the Korean Intellectual Property Office on Apr. 12,2013 and there duly assigned Serial No. 10-2013-0040548.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin film semiconductor deviceincluding a thin film transistor (TFT) and an organic light-emittingdisplay device, and more particularly, to a thin film semiconductordevice including a TFT that maintains a constant electricalcharacteristic and an organic light-emitting display device.

2. Description of the Related Art

Recently, a display device has been settled as an important device amongelectronic products. The display device becomes smaller so as to make iteasy to carry electronic products. There is a limit to the small sizeddisplay device such that demands of diverse users cannot be met. Thus,research into a flexible display device including a rollable or foldableflexible panel has been recently conducted.

When the flexible panel is rolled or folded, the flexible panelelongates in a rolling or folding direction and contracts in a directionperpendicular to the rolling or folding direction. As a result, physicalnumerical values of a channel length and a channel width of a thin filmtransistor (TFT) or the flexible panel may vary, and an electricalcharacteristic of a drain current of the TFT may vary.

SUMMARY OF THE INVENTION

The present invention provides a thin film semiconductor deviceincluding a thin film transistor (TFT) that maintains a constantelectrical characteristic and an organic light-emitting display device.

According to an aspect of the present invention, there is provided athin film semiconductor device including: a flexible substrate; and athin film transistor (TFT) disposed on the substrate and including asemiconductor layer including a source region and a drain region,wherein a part of the source region is spaced apart from the drainregion and partially surrounds the drain region, and wherein a part ofthe drain region is spaced apart from the source region and partiallysurrounds the source region.

The source region and the drain region may have spiral shapes.

The source region and the drain region may have line shapes including afirst edge closer to the center of the TFT and a second edge fartherfrom the center of the TFT, respectively, and include a first arcportion closer to the first edge and having a first curvature radius anda second arc portion closer to the second edge and having a secondcurvature radius greater than the first curvature radius, respectively.

The curvature radius of the second arc portion may be 2 times thecurvature radius of the first arc portion.

The source region and the drain region have may include a firstrectilinear portion extending from the first edge to one end of thefirst arc portion and a second rectilinear portion extending fromanother end of the first arc portion to an opposite direction to adirection in which the first rectilinear portion extends and having thesame length as the first rectilinear portion, respectively, wherein thesecond rectilinear portion of the source region, the first rectilinearportion of the drain region, the first rectilinear portion of the sourceregion, and the second rectilinear portion of the drain region aresequentially and equally spaced apart from each other.

The source region and the drain region may have rectangular spiralshapes.

The source region and the drain region may have line shapes including afirst edge closer to the center of the TFT and a second edge fartherfrom the center of the TFT, respectively, and include a first portionextending from the first edge, a second portion connected to the firstportion and extending in a direction perpendicular to a direction inwhich the first portion extends, a third portion connected to the secondportion and extending in an opposite to the direction in which the firstportion extends, and a fourth portion connected to the third portion andextending in an opposite to a direction in which the second portionextends, respectively.

A length of the first portion may be shorter than a length of the thirdportion.

The source region and the drain region may be rotational and symmetricalto each other.

The semiconductor layer may include a channel region defined as a regionbetween the source region and the drain region, wherein the channelregion includes a channel length defined as a distance between thesource region and the drain region and a channel width defined along adirection perpendicular to the channel length.

The substrate may extend in a first direction and a second directionperpendicular to the first direction, wherein the channel regionincludes a plurality of first portions having channel lengthsperpendicular to the first direction and a plurality of second portionshaving channel lengths in a direction perpendicular to the seconddirection.

The channel lengths may be uniform in a direction of the channel width.

The substrate and the semiconductor layer may be elongatable.

When the substrate elongates in the first direction, the channel lengthsof the plurality of first portions of the channel region decrease, andthe channel lengths of the plurality of second portions of the channelregion increase, and wherein when the substrate elongates in the seconddirection, the channel lengths of the plurality of second portions ofthe channel region decrease, and the channel lengths of the plurality offirst portions of the channel region increase.

The TFT may further include a bottom gate electrode disposed between thesubstrate and the channel region of the semiconductor layer.

The TFT may further include a top gate electrode disposed on the channelregion of the semiconductor layer.

The TFT may further include a bottom gate electrode disposed between thesubstrate and the channel region of the semiconductor layer and a topgate electrode disposed on the channel region of the semiconductorlayer.

The bottom gate electrode and the top gate electrode may be electricallyconnected to each other and have a same electric potential.

The TFT may further include a source electrode electrically connected tothe source region through a first contact plug and a drain electrodeelectrically connected to the drain region through a second contactplug.

The TFT may further include a source electrode connected to the sourceregion and a drain electrode connected to the drain region, and whereinthe source electrode and the drain electrode are disposed to contact thesemiconductor layer on a top surface of the semiconductor layer alongthe semiconductor layer and define the source region and the drainregion, respectively.

The TFT may further include a source electrode connected to the sourceregion and a drain electrode connected to the drain region, and whereinthe source electrode and the drain electrode are disposed to contact thesemiconductor layer on a bottom surface of the semiconductor layer alongthe semiconductor layer and define the source region and the drainregion, respectively.

The semiconductor layer may include at least one silicon semiconductor,an oxide semiconductor, and an organic semiconductor.

According to another aspect of the present invention, there is providedan organic light-emitting display device including: a substrate; a thinfilm transistor (TFT) disposed on the substrate and including asemiconductor layer including a source region and a drain region havingspiral shapes; a bottom electrode electrically connected to the TFT; atop electrode provided on the bottom electrode; and an emission layer(EML) disposed between the bottom electrode and the top electrode andincluding an organic emission layer.

A part of the source region may be spaced apart from the drain regionand partially surrounds the drain region, and wherein a part of thedrain region is spaced apart from the source region and partiallysurrounds the source region.

The source region and the drain region may be rotational and symmetricalto each other.

to another aspect of the present invention, there is provided a thinfilm semiconductor device including: a flexible substrate extending in afirst direction and a second direction perpendicular to the firstdirection; a semiconductor layer disposed on the flexible substrate,including first and second surfaces facing each other, and a channelregion; a source electrode and a drain electrode provided on the firstsurface or the second surface of the semiconductor layer and disposed atboth sides of the channel region along the channel region of thesemiconductor layer; and a gate electrode provided on the first surfaceor the second surface of the semiconductor layer, spaced apart from thesemiconductor layer and overlapping with at least a part of thesemiconductor layer, wherein the channel region includes a channellength defined as a distance between the source region and the drainregion, a plurality of first portions having channel lengthsperpendicular to the first direction, and a plurality of second portionshaving channel lengths in a direction perpendicular to the seconddirection.

When the flexible substrate elongates in the first direction, thechannel lengths of the plurality of first portions of the channel regionmay decrease, and the channel lengths of the plurality of secondportions of the channel region may increase, and when the flexiblesubstrate elongates in the second direction, the channel lengths of theplurality of second portions of the channel region may decrease, and thechannel lengths of the plurality of first portions of the channel regionmay increase.

When the flexible substrate elongates, a change rate of size of thesemiconductor layer according to an elongation direction may be higherthan that of an average channel length of the channel region.

The channel region may be 180 degree rotational and symmetrical.

According to another aspect of the present invention, there is providedan organic light-emitting display device including: a flexible substrateextending in a first direction and a second direction perpendicular tothe first direction; a TFT disposed on the flexible substrate; a bottomelectrode electrically connected to the TFT; a top electrode provided onthe bottom electrode; and an emission layer (EML) disposed between thebottom electrode and the top electrode and including an organic emissionlayer, wherein the TFT includes: a semiconductor layer including achannel region including a channel length and a channel width; a sourceelectrode and a drain electrode provided on the semiconductor layer andspaced apart from each other by the channel length at both sides of thechannel region along the channel width; and a gate electrode overlappingwith the channel region of the semiconductor layer, wherein the channelregion includes a channel length defined as a distance between thesource region and the drain region, a plurality of first portions havingchannel lengths perpendicular to the first direction, and a plurality ofsecond portions having channel lengths in a direction perpendicular tothe second direction.

BRIEF DESCRIPTION OF THE DRAWINGS

A more complete appreciation of the invention, and many of the attendantadvantages thereof, will be readily apparent as the same becomes betterunderstood by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings, in which likereference symbols indicate the same or similar components, wherein:

FIG. 1 is a schematic top plan view illustrating a semiconductor layerof a thin film semiconductor device according to an embodiment of thepresent invention;

FIGS. 2A through 2C are schematic top plan views illustrating a sourceelectrode and a drain electrode that are disposed on the semiconductorlayer of FIG. 1;

FIGS. 3A through 3D are schematic top plan views illustrating variousmodifications of the source electrode and the drain electrode of FIG.2A;

FIGS. 4A through 4C are schematic top plan views illustrating variousmodifications of the source electrode and the drain electrode of FIG.2A;

FIGS. 5A through 5G are cross-sectional views of a thin filmsemiconductor device according to an embodiment of the presentinvention; and

FIG. 6 is a cross-sectional view of an organic light-emitting displaydevice according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully with reference tothe accompanying drawings, in which exemplary embodiments of theinvention are shown. The invention may, however, be embodied in manydifferent forms, and should not be construed as being limited to theembodiments set forth herein. Thus, the invention may include allrevisions, equivalents, or substitutions which are included in theconcept and the technical scope related to the invention.

Like reference numerals in the drawings denote like elements. In thedrawings, the dimension of structures may be exaggerated for clarity.

Furthermore, all examples and conditional language recited herein are tobe construed as being without limitation to such specifically recitedexamples and conditions. Throughout the specification, a singular formmay include plural forms, unless there is a particular descriptioncontrary thereto. Also, terms such as “comprise” or “comprising” areused to specify existence of a recited form, a number, a process, anoperation, a component, and/or groups thereof, not excluding theexistence of one or more other recited forms, one or more other numbers,one or more other processes, one or more other operations, one or moreother components and/or groups thereof. As used herein, the term“and/or” includes any and all combinations of one or more of theassociated listed items. Throughout the specification, while terms“first” and “second” are used to describe various components, it isobvious that the components are not limited to the terms “first” and“second”. The terms “first” and “second” are used only to distinguishbetween each component. As used herein, it will also be understood thatwhen a first feature is referred to as being “connected to”, “combinedwith”, or “interfaced with” a second feature, intervening third featuresmay also be present. Also, throughout the specification, it will also beunderstood that when an element such as layer, region, or substrate isreferred to as being “on”, “connected to” or “coupled with” anotherelement, it can be directly on the other element, or interveningelements may also be present. However, when an element is referred to asbeing “directly on”, “directly connected to” or “directly coupled with”another element, it will be understood that there are no interveningelements.

Unless expressly described otherwise, all terms including descriptive ortechnical terms which are used herein should be construed as havingmeanings that are obvious to one of ordinary skill in the art. Also,terms that are defined in a general dictionary and that are used in thefollowing description should be construed as having meanings that areequivalent to meanings used in the related description, and unlessexpressly described otherwise herein, the terms should not be construedas being ideal or excessively formal.

FIG. 1 is a schematic top plan view illustrating a semiconductor layer10 of a thin film semiconductor device according to an embodiment of thepresent invention.

Referring to FIG. 1, the semiconductor layer 10 includes a source regionSR, a drain region DR, and a channel region CR between the source regionSR and the drain region DR. Although the semiconductor layer 10 in athin film is stacked on a substrate (not shown) and is coupled to otherelements such as a buffer layer, a source electrode, a drain electrode,a gate electrode, a gate insulation layer, etc., the semiconductor layer10 is only illustrated while omitting the other elements for easyunderstanding of the present invention. The semiconductor layer 10 maybe referred to as an active layer.

The semiconductor layer 10 may include an element semiconductor materialincluding a 4 group element such as silicone, germanium, etc. Forexample, the semiconductor layer 10 may be a silicon material layer suchas amorphous silicon or polysilicon. The semiconductor layer 10 may belightly doped with a 3 group element or 5 group element. The sourceregion SR and the drain region DR may be conductive as being heavilydoped with the 3 group element or 5 group element.

The semiconductor layer 10 may include compound semiconductor, inparticular, oxide semiconductor. For example, the semiconductor layer 10may be an oxide semiconductor layer. The oxide semiconductor may includeoxide of at least one material selected from the group consisting ofindium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V),hafnium (Hf), cadmium (Cd), germanium (Gr), chrome (Cr), titanium (Ti),and zinc (Zn). For example, the oxide semiconductor may include gallium(Ga), indium (In), and zinc (Zn) at an element percent (atom %) ratio of2:2:1. However, the present invention is not limited thereto. The oxidesemiconductor may be formed of a quaternary metal oxide such asIn—Sn—Ga—Zn—O-based metal oxide, a ternary metal oxide such asIn—Ga—Zn—O-based metal oxide, In—Sn—Zn—O-based metal oxide,In—Al—Zn—O-based metal oxide, Sn—Ga—Zn—O-based metal oxide, andAl—Ga—Zn—O-based metal oxide, a binary metal oxide such as In—Zn—O-basedmetal oxide, Sn—Zn—O-based metal oxide, Al—Zn—O-based metal oxide,Zn—Mg—O-based metal oxide, Sn—Mg—O-based metal oxide, and In—Mg—O-basedmetal oxide, or a unitary metal oxide such as In—O-based metal oxide,Sn—O-based metal oxide, Zn—O-based metal oxide, Ti—O-based metal oxide,and Cd—O-based metal oxide. In this regard, the In—Ga—Zn—O-based metaloxide may be oxide including at least In, Ga, and Zn, and a compositionratio is not particularly limited. Also, the In—Ga—Zn—O-based metaloxide may include elements other than In, Ga, and Zn.

A thin film transistor (TFT) having the oxide semiconductor as thesemiconductor layer 10 has a characteristic of a high mobility comparedto a conventional silicon (Si) TFT and thus ion doping for an increasein the mobility may not be separately performed. Also, an oxidesemiconductor TFT has a polycrystal and amorphous structure at a roomtemperature, and thus an annealing process may be skipped andaccordingly it is possible to manufacture the oxide semiconductor TFT ata low temperature. Also, the semiconductor layer 10 may be formed bysputtering, and thus oxide semiconductor TFT may be applied to a largearea substrate and advantageously uses an inexpensive material.

The semiconductor layer 10 may an organic semiconductor. For example,the semiconductor layer 10 may be an organic semiconductor layer. Theorganic semiconductor may be a high molecular semiconductor or a lowmolecular semiconductor. For example, the organic semiconductor may beformed of pentacene, tetracene, anthracene, naphthalene, flullerene,alpha-6-thiophene, alpha-4-thiophene, oligo thiophene, perylene and itsderivatives, rubrene and its derivatives, coronene and its derivatives,perylenetetra carboxylic diimide and its derivatives, perylene tetracarboxylic dianhydride and its derivatives, polythiophene and itsderivatives, poly-para-phenylene vinylene and its derivatives,poly-para-phenylene and its derivatives, polyflullerenepoly-para-phenylene vinylene and its derivatives, polythiophene vinyleneand its derivatives, polythiophene-heterocyclic aromatic copolymer andits derivatives, oligoacene of naphthalene and their derivatives,naphthalene tetra carboxylic acid diimide and its derivatives, oligothiophene of alpha-5-thiophene and their derivatives, metal or metalfree phthalocyanines and their derivatives, pyromellitic dianhydride andtheir derivatives, pyromellitic diimide and their derivatives,polyalkylthiophene, polythienylenevinylene, alkylfluorene unit,copolymer of alkylthiophene. However, these materials are exemplary andother organic semiconductors may be employed as materials of thesemiconductor layer 10. In this regard, the semiconductor layer 10 maybe formed by screen printing, printing, spin coating, deep coating, andink spraying but the present invention is not limited thereto. When thesemiconductor layer 10 is the organic semiconductor layer, thesemiconductor layer 10 may include a predetermine functional group. Afunction and characteristic of the semiconductor layer 10 may bemodified in various ways according to a type of the functional group.

The semiconductor layer 10 may be flexible. In addition, thesemiconductor layer 10 extending in a first direction and a seconddirection perpendicular to the first direction may elongate in onedirection. In this regard, the first direction is not limited to ahorizontal direction or a vertical direction of the semiconductor layer10 and may be an optional direction. For example, when a tensile forceof the first direction is applied to the semiconductor layer 10, since acontraction force is applied to the second direction perpendicular tothe first direction, the semiconductor layer 10 may elongate in thefirst direction and contract in the second direction.

When a conventional semiconductor layer elongates in the first directionand contracts in the second direction, a characteristic of a TFTincluding the conventional semiconductor layer varies. A drain currentthat is a core characteristic of the TFT is known to be proportional toan aspect ratio. The aspect ratio means a ratio of a channel width Wwith respect to a channel length L. When the channel length L is definedin the first direction and the channel width W is defined in the seconddirection, if the conventional semiconductor layer elongates in thefirst direction, a problem occurs that the aspect ratio of the TFT maybe greatly reduced and the drain current may be also reduced. To thecontrary, if the conventional semiconductor layer elongates in thesecond direction, a problem also occurs that the aspect ratio of the TFTmay be greatly increased and the drain current may be also increased.

The semiconductor layer 10 of the thin film semiconductor deviceaccording to the present embodiment may include the source region SR anddrain region DR in a spiral shape as shown in FIG. 1. Also, thesemiconductor layer 10 may include the channel region CR defined as aregion between the source region SR and drain region DR. The channelregion CR is a region in which a channel is formed by inverting aconductivity type between the source region SR and drain region DR if anelectrical field is applied by a gate electrode (not shown) that atleast partially overlaps with the channel region CR. The source regionSR and drain region DR may be switched according to a circuitconfiguration. That is, the source region SR may be used as a drain andthe drain region DR may be used as a source.

Although the semiconductor layer 10 further includes an edge region ERthat does not belong to the source region SR, the drain region DR, andthe channel region CR in FIG. 1, the edge region ER may be omittedaccording to patterning of the semiconductor layer 10. The edge regionER may be defined as a region in which no channel is formed although theelectrical field is applied. A boundary between the source region SR anddrain region DR is indicated as a dotted line in FIG. 1 since it is notclear. For example, when an intensity of the electrical field applied tothe gate electrode increases, a channel may be formed in a part of theedge region ER adjacent to the channel region CR.

As shown in FIG. 1, the source region SR and drain region DR may bedisposed in the spiral shape. The source region SR and drain region DRmay be spaced from each other within a predetermined range. The sourceregion SR and drain region DR are spaced apart from each other by afirst distance L in FIG. 1. The first distance L may be referred to asthe channel length L.

As shown in FIG. 1, a spaced distance between the source region SR anddrain region DR may be uniform. The spaced distance between the sourceregion SR and drain region DR may slightly differ according to a planephenomenon between the source region SR and drain region DR. However, amaximum spaced distance between the source region SR and drain region DRmay not exceed 1.5 times a minimum spaced distance therebetween. Forexample, when the source region SR and drain region DR are not curvedshapes but are rectilinear shapes meeting at right angles, the maximumspaced distance may be 2.5 times the minimum spaced distance.

The source region SR and drain region DR may be line shapes includingfirst edges E1S and E1D and second edges E2S and E2D. When a center ofthe semiconductor layer 10 is indicated as a center point C, the firstedges E1S and E1D may be defined as edges adjacent to the center point Cand the second edges E2S and E2D may be defined as edges far from thecenter point C. The source region SR and drain region DR are line shapesand thus a length direction and a width direction perpendicular to thelength direction may be defined. The source region SR and drain regionDR may have thicknesses d in a uniform width direction.

For convenience of explanation, the source region SR may be divided intoa first portion S1 , a second portion S2, and a third portion S3 betweenthe first edge E1S and the second edge E2S. The first portion S1 may bea portion adjacent to the first edge E1S. The third portion S3 may be aportion adjacent to the second edge E2S. The drain region DR may also bedivided into a first portion D1, a second portion D2, and a thirdportion D3 between the first edge E1D and the second edge E2D. The firstportion D1 may be a portion adjacent to the first edge E1D. The thirdportion D3 may be a portion adjacent to the second edge E2D.

As shown in FIG. 1, a part of the source region SR may partiallysurround the drain region DR. More specifically, the third portion S3 ofthe source region SR may surround the first portion D1 of the drainregion DR with respect to the first edge E1S of the source region SR.

A part of the drain region DR may partially surround the source regionSR. More specifically, the third portion D3 of the drain region DR maysurround the first portion S1 of the source region SR with respect tothe first edge E1D of the drain region DR.

The first portion S1 and the second portion S2 of the source region SRmay be referred to as a first arc portion. Also, the third portion S3 ofthe source region SR may be referred to as a second arc portion. Asshown in FIG. 1, a curvature radius of the second arc portion may begreater than that of the first arc portion since the second arc portionneeds to surround a part of the drain region DR.

More specifically, the source region's first arc portion may be a partof a circumference with respect to the first edge E1D of the drainregion DR. The curvature radius of the first arc portion may be adistance L+d between the first edge E1D of the drain region DR and thefirst edge E1S of the source region SR. The second arc portion may be apart of a circumference with respect to the first edge E1S of the sourceregion SR. The curvature radius of the second arc portion may be adistance 2L+2d between the first edge E1S of the source region SR andthe second edge E2D of the drain region DR. The curvature radius of thesecond arc portion may be 2 times the curvature radius of the first arcportion.

The drain region DR may have the same shape as the source region SR. Thefirst portion D1 and the second portion D2 of the drain region DR may bereferred to as the first arc portion. The third portion D3 of the drainregion DR may be referred to as the second arc portion. As shown in FIG.1, the curvature radius of the second arc portion may be greater thanthat of the first arc portion since the second arc portion needs tosurround a part of the source region SR.

More specifically, the drain region's first arc portion may be a part ofa circumference with respect to the first edge E1S of the source regionSR. The curvature radius of the first arc portion may be a distance L+dbetween the first edge E1S of the source region SR and the first edgeE1D of the drain region DR. The second arc portion may be a part of acircumference with respect to the first edge E1D of the drain region DR.The curvature radius of the second arc portion may be a distance 2L+2dbetween the first edge E1D of the drain region DR and the second edgeE2S of the source region SR. The curvature radius of the second arcportion may be 2 times the curvature radius of the first arc portion.

As described above, the channel region CR may be defined as a regionbetween the source region SR and the drain region DR. The channel regionCR may also be a line shape having a uniform width. The channel regionCR may have the channel length L and the channel width W. As describedabove, the channel length L may be defined as a distance between thesource region SR and the drain region DR, and may be uniform as shown inFIG. 1. The channel width W may be a distance defined according to adirection perpendicular to the channel length L. Since an edge of thechannel region CR and the edge region ER is not clear, although thechannel width W may not be exactly measured, as shown in FIG. 1, thechannel width W may be defined as a distance from the second edge E2S ofthe source region SR and the second edge E2D of the drain region DRaccording to a middle points of the source region SR and the drainregion DR.

As described above, the source region SR and the drain region DR havespiral shapes, and thus the channel region CR may also have a spiralshape. However, the spiral shapes of the source region SR and the drainregion DR are spiral shapes in which two lines having one end disposedin the center and another end disposed outside are spaced apart fromeach other, whereas the spiral shape of the channel region CR is aspiral shape formed by a single line having all ends disposed outside.

As a result, the channel region CR may include a plurality of firstportions C1 having channel lengths in a direction perpendicular to thefirst direction and a plurality of second portions C2 having channellengths in a direction perpendicular to the second direction.

When the semiconductor layer 10 elongates and channel lengths of thefirst portions C1 increase, channels lengths of the second portions C2decrease. To the contrary, when channel lengths of the second portionsC2 increase, channel lengths of the first portions C1 decrease. Forexample, when the semiconductor layer 10 elongates in the firstdirection, the semiconductor layer 10 may contract in the seconddirection. As a result, channels lengths of the second portions C2increase, whereas channel lengths of the first portions C1 decrease, andthus an overall change in the channel lengths may be compensated. To thecontrary, when the semiconductor layer 10 elongates in the seconddirection, the semiconductor layer 10 may contract in the firstdirection. As a result, channels lengths of the first portions C1increase, whereas channel lengths of the second portions C2 decrease,and thus an overall change in the channel lengths may be compensated.

Therefore, although the semiconductor layer 10 elongates in anydirections by a tensile force applied from the outside, an averagechannel length by a shape of the channel region CR according to thepresent invention may not greatly change. That is, although thesemiconductor layer 10 elongates 1%, the average channel length maychange at a change rate lower than 1%.

Although the semiconductor layer 10 elongates in any directions, thesemiconductor layer 10 contracts in a direction perpendicular to thechannel width W, the channel width W hardly changes as a whole. Althoughthe semiconductor layer 10 elongates, since the channel width W and theaverage channel length hardly change, an aspect ratio slightly changes,and a current characteristic of a TFT including the semiconductor layer10 hardly changes.

As shown in FIG. 1, the source region SR and the drain region DR mayhave a 180 degree rotational and symmetrical relationship with respectto the center point C. The channel region CR may also be 180 degreerotational and symmetrical with respect to the center point C.

As described above, impurity ions are doped with the source region SRand the drain region DR so that the source region SR and the drainregion DR may have a conductivity higher than the channel region CR. Tothis end, an ion implanting process for doping impurity ions may beperformed only on the source region SR and the drain region DR. In thiscase, a source electrode (not shown) may be electrically connected to apart of the source region SR. A drain electrode (not shown) may beelectrically connected to a part of the drain region DR. The sourceelectrode and the drain electrode may be connected to the source regionSR and the drain region DR, respectively, by using contact plugs.

The source region SR and the drain region DR may be limited by thesource electrode (not shown) and the drain electrode (not shown). Thatis, the source region SR is a region where the semiconductor layer 10contacts the source electrode, and the drain region DR is a region wherethe semiconductor layer 10 contacts the drain electrode. In this regard,the source electrode and the drain electrode may be formed of aconductive material such as a silver nano wire, a carbon nano tube,graphene, and ITO. The source electrode and the drain electrode may beelongatable transparent conductors. Another material layer for anotherpurpose, for example, to reduce a contact resistance, may be disposedbetween the semiconductor layer 10 and the source electrode and betweenthe semiconductor layer 10 and the drain electrode.

For better understanding of the present invention, various embodimentsincluding a source electrode and a drain electrode disposed on thesemiconductor layer 10 instead of the source region SR and the drainregion DR that are included in the semiconductor layer 10 are describedbelow. The source electrode and the drain electrode may respectivelypresent a source region and a drain region. When the source electrodeand the drain electrode are connected to the source region and the drainregion by using contact plugs, the source electrode and the drainelectrode present the source region and the drain region havingconductivity in the semiconductor layer 10.

Line V-V of FIG. 1 will be described later with respect to FIGS. 5Athrough 5G.

FIGS. 2A through 2C are schematic top plan views illustrating a sourceelectrode and a drain electrode that are disposed on the semiconductorlayer 10 of FIG. 1. FIG. 2A shows the semiconductor layer 10 that hasnot been elongated in any direction. FIG. 2B shows a semiconductor layer10′ that is elongated in a second direction. FIG. 2C shows asemiconductor layer 10″ that is elongated in a first direction.

Referring to FIG. 2A, the semiconductor layer 10 includes the sourceregion SR, the channel region CR, and the drain region DR. A sourceelectrode SE is disposed on the source region SR and connected to asource wire SW. A drain electrode DE is disposed on the drain region DRand connected to a drain wire DW. The present invention is not limitedto a point at which the source wire SW and the drain wire DW areconnected to the source electrode SE and the drain electrode DE. Thesemiconductor layer 10 has not been elongated in any direction.

Although not shown in FIG. 2A, the semiconductor layer 10 may bedisposed on a substrate (not shown) and include a bottom surface facingthe substrate and a top surface opposite to the bottom surface. Asshown, the source electrode SE and the drain electrode DE may bedisposed on the semiconductor layer 10. More specifically, the sourceelectrode SE and the drain electrode DE may be disposed on the bottomsurface of the semiconductor layer 10 or the top surface thereof.

As described with reference to FIG. 1, the channel region CR may bedefined as a region between the source region SR and the drain region DRand have the uniform channel length L. The channel region CR may includethe plurality of first portions C1 having channel lengths in a directionperpendicular to a first direction and the plurality of second portionsC2 having channel lengths in a direction perpendicular to a seconddirection.

Channel lengths of the first portions C1 may be denoted as L1 a. Channellengths of the second portions C2 may be denoted as L2 a. However, allchannel lengths of the first portions C1 and the second portions C2 maybe uniform as L. Thus, an average channel length may be L.

Referring to FIG. 2B, a semiconductor layer 10′ is elongated in thesecond direction. If a material elongates, since the material contractsin a direction perpendicular to an elongated direction, the materialcontracts in the first direction. As a result, the first portions C1′ ofthe channel region CR elongate in the second direction, and the secondportions C2′ contract in the first direction. Thus, channel lengths ofthe first portions C1′ increase to L1 b, and channel lengths of thesecond portions C2′ decrease to L2 b. As the semiconductor layer 10′elongates, channel lengths of the first portions C1′ increase, whereaschannel lengths of the second portions C2′ decrease, and thus an averagechannel length hardly changes from L. An area occupied by the firstportions C1′ and an area occupied by the second portions C2′ may beadjusted such that the average channel length becomes L.

Referring to FIG. 2C, the semiconductor layer 10″ elongates in the firstdirection. If a material elongates, since the material contracts in adirection perpendicular to an elongated direction, the materialcontracts in the second direction. As a result, the second portions C2″of the channel region CR elongate in the first direction, and the firstportions C1″ contract in the second direction. Thus, channel lengths ofthe second portions C2″ increase to L2 c, and channel lengths of thefirst portions C1″ decrease to L1 c. As the semiconductor layer 10″elongates, channel lengths of the second portions C2″ increase, whereaschannel lengths of the first portions C1″ decrease, and thus an averagechannel length hardly changes from L. An area occupied by the firstportions C1″ and an area occupied by the second portions C2″ may beadjusted such that the average channel length becomes L.

FIGS. 3A through 3D are schematic top plan views illustrating variousmodifications of the source electrode and the drain electrode of FIG.2A. Elements of the modifications of FIGS. 3A through 3D aresubstantially similar to those of FIG. 2A, and thus differencestherebetween will now be described.

Referring to FIG. 3A, the source electrode SE and the drain electrode DEare disposed on a semiconductor layer 10 a. For better understanding ofthe present invention, the source region SR and the drain region DR arenot shown. However, details of the source region SR and the drain regionDR such as locations or sizes will be understood by one of ordinaryskill in the art with reference to FIGS. 1 and 2A.

The source wire SW and the drain wire DW of FIG. 2A are connected in themiddle of the source electrode SE and the drain electrode DE, whereas inFIG. 3A, the source wire SW is directly connected to the sourceelectrode SE in the second edge E2S and the drain wire DW is directlyconnected to the drain electrode DE in the second edge E2D. The sourcewire SW and the drain wire DW may be modified in various ways and may beconnected at locations other than the second edges E2S and E2D in otherdirections. The source wire SW and the drain wire DW may be connected tothe source electrode SE and the drain electrode DE through contact plugs(not shown).

Referring to FIG. 3B, the source electrode SE and the drain electrode DEare disposed on the semiconductor layer 10 b. The source electrode SE ofFIG. 3B is longer than the source electrode of FIG. 2A, and a greaterpart thereof surrounds the drain electrode DE than that of the sourceelectrode SE of FIG. 2A. In terms of a numerical value, if the sourceelectrode SE of FIG. 2A surrounds the drain electrode DE atapproximately 270 degrees, whereas the source electrode SE of FIG. 3Asurrounds the drain electrode DE at approximately 360 degrees.

The drain electrode DE of FIG. 3B is longer than the drain electrode DEof FIG. 2A, and a greater part thereof surrounds the source electrode SEthan that of the drain electrode DE of FIG. 2A. The drain electrode DEof FIG. 3A surrounds the source electrode SE at approximately 360degrees.

The present invention is not limited to the shape of FIG. 3B. The sourceelectrode SE and the drain electrode DE may surround a center point at agreater number of frequencies. That is, the source electrode SE and thedrain electrode DE may surround the center point at angles of such as540 degrees and 720 degrees.

Referring to FIG. 3C, the source electrode SE and the drain electrode DEare disposed on a semiconductor layer 10 c. When the source electrode SEand the drain electrode DE of FIG. 3C are compared to the sourceelectrode SE and the drain electrode DE of FIG. 3A, the source electrodeSE and the drain electrode DE of FIG. 3C further include first andsecond rectilinear portions SS1, SS2 of the source electrode SE andfirst and second rectilinear portions D1, DS2 of the drain electrode DE.That is, the source electrode SE disposed on the semiconductor layer 10c may include the first rectilinear portion SS1, a first arc portionSA1, the second rectilinear portion SS2, and a second arc portion SA2that are sequentially connected between the first edge E1S and thesecond edge E2S. The drain electrode DE may include the firstrectilinear portion DS1, a first arc portion DA1, the second rectilinearportion DS2, and a second arc portion DA2 that are sequentiallyconnected between the first edge E1D and the second edge E2D.

As described with reference to FIG. 1 above, the first arc portion SA1of the source electrode SE may be a part of a circumference with respectto the first edge E1D of the drain electrode DE, and the first arcportion DA1 of the drain electrode DE may be a part of a circumferencewith respect to the first edge E1S of the source electrode SE. Thesecond arc portion SA2 of the source electrode SE may be a part of acircumference with respect to the first edge E1S of the source electrodeSE like the first arc portion DA1 of the drain electrode DE, and thesecond arc portion DA2 of the drain electrode DE may be a part of acircumference with respect to the first edge E1D of the drain electrodeDE like the first arc portion SA1 of the source electrode SE.

The first rectilinear portion SS1 of the source electrode SE may connectthe first edge E1S and one end of the first arc portion SA1. The secondrectilinear portion SS2 of the source electrode SE may connect anotherend of the first arc portion SA1 and one end of the second edge E2S. Thefirst rectilinear portion DS1 of the drain electrode DE may connect thefirst edge E1D and one end of the first arc portion DA1. The secondrectilinear portion DS2 of the drain electrode DE may connect anotherend of the first arc portion DA1 and one end of the second arc portionDA2.

The first rectilinear portion SS1 and the second rectilinear portion SS2of the source electrode SE and the first rectilinear portion DS1 and thesecond rectilinear portion DS2 of the drain electrode DE may have thesame lengths and extend in the same direction. The second rectilinearportion SS2 of the source electrode SE, the first rectilinear portionDS1 of the drain electrode DE, the first rectilinear portion SS1 of thesource electrode SE, and the second rectilinear portion DS2 of the drainelectrode DE may be spaced apart from each other by a uniform gap.

Since the source electrode SE and the drain electrode DE further includethe first and second rectilinear portions SS1, SS2 and DS1, DS2, areasof second portions C2′ of the channel region CR having channel lengthsin a direction perpendicular to a second direction may increase.Accordingly, change levels of channel lengths of the first portions C1and opposite change levels of channel lengths of the second portions C2′may be exactly consistent with each other. Although the first and secondrectilinear portions SS1, SS2 and DS1, DS2 elongate in any directions,lengths thereof may be selected such that an average channel length maybe uniform to L.

Referring to FIG. 3D, the source electrode SE and the drain electrode DEare disposed on a semiconductor layer 10 d. When the source electrode SEand the drain electrode DE disposed on the semiconductor layer 10 d arecompared to the source electrode SE and the drain electrode DE of FIG.3B, the source electrode SE and the drain electrode DE of FIG. 3D rotateby 90 degrees counterclockwise and further include first through thirdrectilinear portions SS1-SS3 and DS1-DS3.

That is, the source electrode SE disposed on the semiconductor layer 10d may include the first rectilinear portion SS1, the first arc portionSA1, the second rectilinear portion SS2, the second arc portion SA2, andthe third rectilinear portion SS3 that are sequentially connectedbetween the first edge E1S and the second edge E2S. Also, the drainelectrode DE may include the first rectilinear portion DS1, the firstarc portion DA1, the second rectilinear portion DS2, the second arcportion DA2, and the third rectilinear portion DS3 that are sequentiallyconnected between the first edge E1D and the second edge E2D.

As shown in FIG. 3D, the source electrode SE and the drain electrode DEmay be modified in various ways.

FIGS. 4A through 4C are schematic top plan views illustrating variousmodifications of the source electrode and the drain electrode of FIG.2A. Elements of the modifications of FIGS. 4A through 4C aresubstantially similar to those of FIG. 2A, and thus differencestherebetween will now be described.

Referring to FIG. 4A, the source electrode SE and the drain electrode DEare disposed on a semiconductor layer 10 e. The source electrode SE andthe drain electrode DE may have rectangular spiral shapes as shown inFIG. 4A. The semiconductor layer 10 e may extend in a first directionand a second direction perpendicular to the first direction. An oppositedirection to the first direction may be referred to as a thirddirection. An opposite direction to the second direction may be referredto as a fourth direction. The source wire SW is connected to the sourceelectrode SE. The drain wire DW is connected to the drain electrode DE.

More specifically, the source electrode SE may have a line shape havingthe first edge E1S and the second edge E2S, and the drain electrode DEmay have a line shape having the first edge E1D and the second edge E2D.

The source electrode SE may include the first portion SS1 extending fromthe first edge E1S to the second direction, the second portion SS2connected to the first portion SS1 and extending in the third direction,a third portion SS3 connected to the second portion SS2 and extending inthe fourth direction, and a fourth portion SS4 connected to the thirdportion SS3, extending in the first direction, and ending in the secondedge E2S. Although the first through fourth portions SS1˜SS4 may beconnected to each other via curved portions as shown, this is exemplaryand may be connected to each other at right angles. All the firstthrough fourth portions SS1˜SS4 have rectangular spiral shapes, and thusthe third portion SS3 is disposed outside compared to the first portionSS1, and the fourth portion SS4 is disposed outside compared to thesecond portion SS2. Therefore, the third portion SS3 and the fourthportion SS4 have lengths longer than the first portion SS1 and thesecond portion SS2.

The drain electrode DE may also include the first portion DS1 extendingfrom the first edge E1D to the fourth direction, the second portion DS2connected to the first portion DS1 and extending in the first direction,a third portion DS3 connected to the second portion DS2 and extending inthe second direction, and a fourth portion DS4 connected to the thirdportion DS3, extending in the third direction, and ending in the secondedge E2D.

The semiconductor layer 10 e may include the channel region CR betweenthe source electrode SE and the drain electrode DE. The channel regionCR may have a channel length that varies from L to L′ according to itslocation.

The channel region CR may include the first portions C1 having channellengths in the direction perpendicular to the first direction and thesecond portions C2 having channel lengths in the direction perpendicularto the second direction. Parts of the first portions C1 and secondportions C2 are exemplary shown in FIG. 4A.

As described above, since the semiconductor layer 10 e extends, channellengths of the first portions C1 and channel lengths of the secondportions C2 change the other way around, and thus an average channellength does not greatly change as a whole.

Referring to FIG. 4B, the source electrode SE and the drain electrode DEare disposed on a semiconductor layer 10 f. The source wire SW isconnected to the second edge E2S of the source electrode SE. The drainwire DW is connected to the second edge E2D of the drain electrode DE.In this case, the source wire SW and the source electrode SE and thedrain wire DW and the drain electrode DE may be concurrently formedduring the same process.

As described with reference to FIG. 4B above, the source wire SW and thedrain wire DW may be connected to any portions of the source electrodeSE and the drain electrode DE. Although not shown, the source electrodeSE and the drain electrode DE may further include pads for connectingthe source electrode SE and the drain electrode DE to the source wire SWand the drain wire DW.

Referring to FIG. 4C, the source electrode SE and the drain electrode DEare disposed on the semiconductor layer 10 g. When the source electrodeSE and the drain electrode DE that are disposed on the semiconductorlayer 10 g are compared to the source electrode SE and the drainelectrode DE of FIG. 4A, lengths of the first and third portions SS1 andSS3 and the source electrode SE are increased, and accordingly, lengthsof the drain electrode DE and the first and third portions DS1 and theDS3 are increased.

As described with reference to FIG. 4C above, areas of the secondportions C2 of the channel region CR may change by changing lengths ofthe first and third portions SS1, SS3 and DS1, DS3. As a result, channellengths of the second portions C2 may reversely change in accordancewith changes in channel lengths of the first portions C1 of the channelregion CR. Thus, lengths of the first and third portions SS1, SS3 andDS1, DS3 may be adjusted such that the average channel length does notchange.

FIGS. 5A through 5G are cross-sectional views of thin film semiconductordevices 100 a through 100 g according to embodiments of the presentinvention.

Referring to FIG. 5A, the thin film semiconductor device 100 a includesa substrate Sub and a thin film transistor TFTa disposed on thesubstrate Sub. The thin film transistor TFTa may include thesemiconductor layer 10, the gate electrode G, the source electrode SE,and the drain electrode DE. FIG. 5A is a cross-sectional viewillustrating the thin film semiconductor device 100 a, taken along lineV-V of FIG. 1.

The substrate Sub may be a flexible substrate. For example, thesubstrate Sub may be formed of a plastic material having excellent heatresistance and durability such as polyimide (PI), polyethyleneterephthalate (PET), polyethylene naphtalate (PEN), polycarbonate (PC),polyarylate (PAR), polyetherimide (PEI), and polyethersulphone (PES).However, the present invention is not limited thereto, and the substrateSub may use various flexible materials such as a metal foil or thin filmglass. The substrate Sub may elongate in any direction according to anexternal tensile force.

Meanwhile, the substrate Sub may be a rigid substrate and may be formedof a transparent glass material having silicon oxide (SiO₂) as a maincomponent.

The semiconductor layer 10 may be disposed on the substrate Sub. Asdescribed with reference to FIG. 1 above, the semiconductor layer 10 maybe an element semiconductor layer including a 4-group element such assilicon and germanium. In this case, the source region SR and the drainregion DR may be doped with impurity ions and have conductivity. Thechannel region CR may be lightly doped with impurity ions. In this case,conductivity of impurity ions doped on the channel region CR may beopposite to that of impurity ions doped on the source region SR and thedrain region DR.

The semiconductor layer 10 may be a compound semiconductor layer formedof a compound semiconductor such as an oxide semiconductor or an organicsemiconductor layer formed of an organic semiconductor.

Although not shown, a buffer layer (not shown) may be disposed betweenthe semiconductor layer 10 and the substrate Sub to prevent impuritiesfrom introducing from the substrate Sub.

A gate insulation layer G1 including an insulation material such as,silicon oxide, silicon nitride, and/or silicon oxynitride, is formed onthe semiconductor layer 10. The gate electrode G may be disposed on apredetermined region of the gate insulation layer G1. The gate electrodeG may be connected to a gate line (not shown) to which a control signalfor controlling the thin film transistor TFTa is applied.

An interlayer insulation layer ILD may be disposed on the gate electrodeG. The interlayer insulation layer ILD may include a contact hole forexposing the source region SR and the drain region DR of thesemiconductor layer 10. The source electrode SE and the drain electrodeDE may be electrically connected to the source region SR and the drainregion DR, respectively, through contact plugs CP buried in the contacthole of the interlayer insulation layer ILD. The above-formed thin filmtransistor TFTa may be protected by being covered by a passivation layerPSV.

Referring to FIG. 5B, the thin film semiconductor device 100 b, takenalong the line V-V of FIG. 1, includes the substrate Sub and a thin filmtransistor TFTb disposed on the substrate Sub. The thin film transistorTFTb may include a semiconductor layer 10-1, the gate electrode G, thesource electrode SE, and the drain electrode DE.

The semiconductor layer 10-1 and the gate electrode G may besequentially stacked on the substrate Sub. The substrate Sub may be anelongatable plastic substrate. The semiconductor layer 10-1 may be anelongatable oxide semiconductor layer or organic semiconductor layer.

The source electrode SE and the drain electrode DE may be disposedbetween the substrate Sub and the semiconductor layer 10-1. Othermaterial layers having conductivity may be disposed between the sourceelectrode SE, the drain electrode DE, and the semiconductor layer 10-1.

The gate insulation layer GI may be disposed between the semiconductorlayer 10-1 and the gate electrode G. Although the gate insulation layerGI may be shown as a single layer, the gate insulation layer GI may havea stack structure of a plurality of insulation materials.

The above-formed thin film transistor TFTb may be covered by theinterlayer insulation layer ILD.

Referring to FIG. 5C, the thin film semiconductor device 100 c, takenalong the line V-V of FIG. 1, includes the substrate Sub and a thin filmtransistor TFTc disposed on the substrate Sub. The thin film transistorTFTc may include a semiconductor layer 10-2, the gate electrode G, thesource electrode SE, and the drain electrode DE.

The semiconductor layer 10-2 and the gate electrode G may besequentially stacked on the substrate Sub. A buffer layer (not shown)may be disposed between the substrate Sub and the semiconductor layer10-2. The source electrode SE and the drain electrode DE and the gateinsulation layer GI that covers the source electrode SE and the drainelectrode DE may be disposed between the semiconductor layer 10-2 andthe gate electrode G. The above-formed thin film transistor TFTc may becovered by the interlayer insulation layer ILD.

Referring to FIG. 5D, the thin film semiconductor device 100 d, takenalong the line V-V of FIG. 1, includes the substrate Sub and a thin filmtransistor TFTd disposed on the substrate Sub. The thin film transistorTFTd may include a semiconductor layer 10-3, the gate electrode G, thesource electrode SE, and the drain electrode DE.

The gate electrode G and the semiconductor layer 10-3 may besequentially stacked on the substrate Sub. A buffer layer (not shown)may be disposed between the substrate Sub and the gate electrode G. Thegate insulation layer GI may be disposed to cover the gate electrode G.The source electrode SE and the drain electrode DE may be disposedbetween the gate insulation layer GI and the semiconductor layer 10-3.The above-formed thin film transistor TFTd may be covered by theinterlayer insulation layer ILD.

Referring to FIG. 5E, the thin film semiconductor device 100 e, takenalong the line V-V of FIG. 1, includes the substrate Sub and a thin filmtransistor TFTe disposed on the substrate Sub. The thin film transistorTFTe may include a semiconductor layer 10-4, the gate electrode G, thesource electrode SE, and the drain electrode DE.

The gate electrode G and the semiconductor layer 10-4 may besequentially stacked on the substrate Sub. A buffer layer (not shown)may be disposed between the substrate Sub and the gate electrode G. Thegate insulation layer GI may be disposed between the gate electrode Gand the semiconductor layer 10-4. The source electrode SE and the drainelectrode DE may be disposed on the semiconductor layer 10-4. The sourceelectrode SE and the drain electrode DE may be covered by the interlayerinsulation layer ILD.

Referring to FIG. 5F, the thin film semiconductor device 100 f, takenalong the line V-V of FIG. 1, includes the substrate Sub and a thin filmtransistor TFTf disposed on the substrate Sub. The thin film transistorTFTf may include a semiconductor layer 10-5, a bottom gate electrode G1,a top gate electrode G2, the source electrode SE, and the drainelectrode DE.

The bottom gate electrode G1, the semiconductor layer 10-5, and the topgate electrode G2 may be sequentially stacked on the substrate Sub. Abuffer layer (not shown) may be disposed between the substrate Sub andthe bottom gate electrode G1.

A bottom gate insulation layer GI1 may be disposed between the bottomgate electrode G1 and the semiconductor layer 10-5. A top gateinsulation layer GI2 may be disposed between the top gate electrode G2and the semiconductor layer 10-5. A thickness of the bottom gateinsulation layer GI1 disposed below a channel region of thesemiconductor layer 10-5 may be t1. A thickness of the top gateinsulation layer GI2 disposed above the channel region of thesemiconductor layer 10-5 may be t2.

The source electrode SE and the drain electrode DE may be disposedbetween the bottom gate insulation layer GI1 and the semiconductor layer10-5. The top gate electrode G2 may be covered by the interlayerinsulation layer ILD.

The bottom gate electrode G1 and the top gate electrode G2 may beelectrically connected to each other and have a common electricpotential. That is, the thin film semiconductor device 100 f may becontrolled by a voltage commonly applied to the bottom gate electrode G1and the top gate electrode G2. The thin film semiconductor device 100 fmay be flexible. When the thin film semiconductor device 100 f bends atthe channel region, a distance t1 from the semiconductor layer 10-5 tothe bottom gate electrode G1 and a distance t2 from the semiconductorlayer 10-5 to the top gate electrode G2 may vary. As a result, anintensity of an electric field applied to the channel region of the thinfilm semiconductor device 100 f from the bottom gate electrode G1 andthe top gate electrode G2 may vary.

However, in the thin film semiconductor device 100 f of the presentinvention, since the bottom gate electrode G1 and the top gate electrodeG2 are disposed on a bottom portion and a top portion of thesemiconductor layer 10-5, respectively, when the distance t1 from thesemiconductor layer 10-5 to the bottom gate electrode G1 decreases, thedistance t2 from the semiconductor layer 10-5 to the top gate electrodeG2 increases, and thus the intensity of the electric field applied tothe channel region of the thin film semiconductor device 100 f from thebottom gate electrode G1 and the top gate electrode G2 may be uniform,and an electrical characteristic of the thin film semiconductor device100 f may not greatly change. The distance t1 from the semiconductorlayer 10-5 to the bottom gate electrode G1 and the distance t2 from thesemiconductor layer 10-5 to the top gate electrode G2 may be the same.

Referring to FIG. 5G, the thin film semiconductor device 100 g, takenalong the line V-V of FIG. 1, includes the substrate Sub and a thin filmtransistor TFTg disposed on the substrate Sub. The thin film transistorTFTg may include a semiconductor layer 10-6, a bottom gate electrode G1,a top gate electrode G2, the source electrode SE, and the drainelectrode DE.

The bottom gate electrode G1, the semiconductor layer 10-6, and the topgate electrode G2 may be sequentially stacked on the substrate Sub. Abuffer layer (not shown) may be disposed between the substrate Sub andthe bottom gate electrode G1.

The bottom gate insulation layer GI1 may be disposed between the bottomgate electrode G1 and the semiconductor layer 10-6. The top gateinsulation layer GI2 may be disposed between the top gate electrode G2and the semiconductor layer 10-6. The source electrode SE, and the drainelectrode DE may be disposed between the top gate insulation layer GI2and the semiconductor layer 10-6. The top gate insulation layer GI2 maybe covered by interlayer insulation layer ILD. The bottom gate electrodeG1 and the top gate electrode G2 may be electrically connected to eachother and have a common electric potential.

At least a part of the gate electrodes G, G1, and G2 of FIGS. 5A through5G may overlap with channel regions of the semiconductor layers 10 and10-1 through 10-6. A part of the gate electrodes G, G1, and G2 mayoverlap with the semiconductor layers 10 and 10-1 through 10-6 or thegate electrodes G, G1, and G2 may overlap with a part of thesemiconductor layers 10 and 10-1 through 10-6. That is, areas of thegate electrodes G, G1, and G2 may be greater or smaller than or the sameas those of the semiconductor layers 10 and 10-1 through 10-6.

FIG. 6 is a cross-sectional view of an organic light-emitting displaydevice 200 according to an embodiment of the present invention.

The organic light-emitting display device 200 according to an embodimentof the present invention may include the semiconductor layers 10 and10-1 through 10-6 or the thin film semiconductor devices 100 a through100 g of FIGS. 1 through 5G. FIG. 6 exemplary shows a cross section ofthe organic light-emitting display device 200 employing the thin filmsemiconductor device 100 d of FIG. 5D. However, this is exemplary andvarious modifications may be possible.

Referring to FIG. 6, the organic light-emitting display device 200includes a thin film transistor TFT and an intermediate layer 265including an organic emission layer disposed between a bottom electrode255 and a top electrode 270.

A buffer layer 215 may be disposed on a substrate 210 to preventimpurities from introducing from the substrate 210. The substrate 210may be formed of glass, silicon, plastic, or metal and may be a flexiblesubstrate.

An electrode material layer may be formed on the buffer layer 215. Agate electrode 220 may be formed on the buffer layer 215 by patterningthe gate electrode material layer. The gate electrode 220 may be formedof metal such as MoW, Al, Cr, and Al/Cr or conductive polymer. Forexample, the gate electrode 220 may be formed of a conductive materialsuch as silver nano wire, carbon nano tube, graphene, and ITO. The gateelectrode 220 may be a transparent electrode and elongatable.

A gate insulation layer 225 may be stacked on a front surface of thesubstrate 210 to cover the gate electrode 220. For example, the gateinsulation layer 225 may be formed of an inorganic insulation materialsuch as oxide, nitride, oxynitride, or a combination of these. Forexample, the gate insulation layer 225 may be formed of an organicinsulation material such as benzocyclobutene (BCB), polyimide,polyvinylphenol, parylene, epoxy, and poly vinyl chloride.

An electrode material layer may be stacked on the front surface of thesubstrate 210 to cover the gate insulation layer 225. The electrodematerial layer may be patterned with the source electrode SE and thedrain electrode DE of one of FIGS. 2A through 4C. As shown in FIG. 6, asource electrode 230 and a drain electrode 235 may be formed on the gateinsulation layer 225, and the gate electrode 220 may be disposed below aspace between the source electrode 230 and the drain electrode 235.

The source electrode 230 and the drain electrode 235 may be formed ofmetal such as molybdenum (Mo), chrome (Cr), tungsten (W),aluminum-neodymium (Al—Nd), titanium (Ti), molybdenum tungsten (MoW),and aluminum (Al). The source electrode 230 and the drain electrode 235may be formed of conductive polymer. For example, the source electrode230 and the drain electrode 235 may be formed of the conductive materialsuch as silver nano wire, carbon nano tube, graphene, and ITO, and maybe transparent or elongatable.

A semiconductor layer 240 may be disposed between the source electrode230 and the drain electrode 235 and formed on the gate electrode 220.The semiconductor layer 240 may over the source electrode 230 and thedrain electrode 235. The semiconductor layer 240 includes a channelregion in which a channel is formed when the thin film transistor TFToperates. The channel region is a part of the semiconductor layer 240between the source electrode 230 and the drain electrode 235.

The semiconductor layer 240 may be an element semiconductor layer, acompound semiconductor layer, or an organic semiconductor layer. Aninterlayer insulation layer 245 may be disposed on the front surface ofthe substrate 210 in which the semiconductor layer 240 is formed. Theinterlayer insulation layer 245 may include an inorganic insulationmaterial or an organic insulation material. The interlayer insulationlayer 245 may protect the thin film transistor TFT.

A contact plug 250 that passes through the interlayer insulation layer245 may be used to form the bottom electrode 255 connected to the drainelectrode 235 on the interlayer insulation layer 245. Although thebottom electrode 255 is connected to the drain electrode 235 in FIG. 6,this is exemplary. The bottom electrode 255 may be a transparentelectrode or a reflective electrode.

The bottom electrode 255 may be a transparent electrode or a reflectiveelectrode. When the bottom electrode 255 is formed as a transparentelectrode, the bottom electrode 255 may include ITO, IZO, ZnO, or In₂O₃.Also, when the bottom electrode 255 is formed as a reflective electrode,the bottom electrode 255 may have a multi-stack structure including afirst layer that is formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, orcompound of any of these, and a second layer that is formed on the firstlayer and that includes ITO, IZO, ZnO, or In₂O₃.

A pixel-defining layer (PDL) 260 that defines a pixel by exposing a partof the bottom electrode 255 may be disposed on the interlayer insulationlayer 245. The intermediate layer 265, including an EML, may be formedon the bottom electrode 255 that is exposed through pixel-defining layer(PDL) 260.

The top electrode 270 may be stacked on an entire surface of thesubstrate 210. In this regard, the top electrode 270 may be formed as atransparent electrode or a reflective electrode. When the top electrode270 is formed as a transparent electrode, the top electrode 270 mayinclude a first layer that is formed of Li, Ca, LiF/Ca, LiF/Al, Al, Mg,or a compound of any of these, and a second layer that is formed on thefirst layer and that includes ITO, IZO, ZnO, or In₂O₃. In this regard,the second layer may be formed as an auxiliary electrode or a buselectrode line. When the top electrode 270 is formed as a reflectiveelectrode, the aforementioned Li, Ca, LiF/Ca, LiF/Al, Al, Mg, or acompound of any of these is completely deposited.

The intermediate layer 265 that is interposed between the bottomelectrode 255 and the top electrode 270 may include a small moleculeorganic material or a polymer organic material.

When the intermediate layer 265 includes a small molecule organicmaterial, the intermediate layer 265 may have a structure in which ahole injection layer (HIL), a hole transport layer (HTL), an emissionlayer (EML), an electron transport layer (ETL), and an electroninjection layer (EIL) are singularly or multiply stacked.

Also, the intermediate layer 265 may be formed of various organicmaterials including copper phthalocyanine (CuPc),N,N′-Di(naphthalene-1-yl)-N,N′-diphenyl-benzidine (NPB),tris-8-hydroxyquinoline aluminum)(Alq3), or the like, by a vacuumdeposition method using masks.

When the intermediate layer 265 includes a polymer organic material, theintermediate layer 265 may have a structure of an HTL and an EML, and inthis regard, the HTL may be formed of poly(3,4-ethylenedioxythiophene)(PEDOT), and the EML may be formed of a poly-phenylenevinylene(PPV)-based material or a polyfluorene-based material.

An encapsulation layer 280 may be formed on the top electrode 270. Theencapsulation layer 280 may have a structure in which an inorganic layeror an inorganic layer and organic layer are alternatively stacked.

If a flexible device is rolled or folded in a direction, a tensile forceis generated in the rolled or folded direction, whereas, according tothe one or more embodiments of the present invention, a channel lengthincreases in the rolled or folded direction and a channel length in adirection perpendicular to the rolled or folded direction decreases,thereby constantly maintaining an average channel length. Thus, althoughthe flexible device is rolled or folded in a direction, an electricalcharacteristic of a TFT may be constantly maintained.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

What is claimed is:
 1. A thin film semiconductor device, comprising: aflexible elongatable substrate, the substrate being elongatable in afirst direction and the substrate being elongatable in a seconddirection perpendicular to the first direction, the flexible elongatablesubstrate being comprised of a plastic material; and a thin filmtransistor (TFT) disposed on the substrate and comprising a flexiblesemiconductor layer comprising a source region, a drain region and achannel region arranged between the source region and the drain region,wherein a channel length being a distance between the source region andthe drain region, wherein a part of the source region is spaced apartfrom the drain region and partially surrounds the drain region, andwherein a part of the drain region is spaced apart from the sourceregion and partially surrounds the source region, wherein the channelregion comprises a plurality of first portions having channel lengthsextending perpendicular to the first direction and a plurality of secondportions having channel lengths extending perpendicular to the seconddirection, wherein an area occupied by the first portions and an areaoccupied by the second portions are adjusted so that an average channellength of the thin film transistor remains unchanged upon the thin filmsemiconductor device being rolled, folded or subjected to tensileforces.
 2. The thin film semiconductor device of claim 1, wherein thesource region, the drain region and the channel region each have spiralshapes, the source and drain regions being regions of the semiconductorlayer that have a higher doping concentration than other areas of thesemiconductor layer.
 3. The thin film semiconductor device of claim 1,wherein the source region and the drain region have line shapes eachcomprising a first edge closer to a center of the TFT and a second edgefarther from the center of the TFT, respectively, and each comprising afirst arc portion closer to the first edge and having a first curvatureradius and a second arc portion closer to the second edge and having asecond curvature radius greater than the first curvature radius,respectively, the source region and the drain region have 180 degreerotational and symmetrical relationship with respect to a center pointof the semiconductor layer.
 4. The thin film semiconductor device ofclaim 3, wherein the source region and the drain region each comprise afirst rectilinear portion extending from the first edge to one end ofthe first arc portion and a second rectilinear portion extending fromanother end of the first arc portion to an opposite direction to adirection in which the first rectilinear portion extends and having thesame length as the first rectilinear portion, respectively, wherein thesecond rectilinear portion of the source region, the first rectilinearportion of the drain region, the first rectilinear portion of the sourceregion, and the second rectilinear portion of the drain region aresequentially and equally spaced apart from each other.
 5. The thin filmsemiconductor device of claim 1, wherein the source region, the drainregion and the channel region each have rectangular spiral shapes. 6.The thin film semiconductor device of claim 1, wherein the source regionand the drain region have line shapes each comprising a first edgecloser to a center of the TFT and a second edge farther from the centerof the TFT, respectively, and each comprising a first portion extendingfrom the first edge, a second portion connected to the first portion andextending in a direction perpendicular to a direction in which the firstportion extends, a third portion connected to the second portion andextending in an opposite to the direction in which the first portionextends, and a fourth portion connected to the third portion andextending in an opposite to a direction in which the second portionextends, respectively, wherein lengths of the first and third portionsare adjusted so that an average channel length does not change upon thethin film semiconductor device being rolled, folded or subjected totensile forces.
 7. The thin film semiconductor device of claim 1,wherein the channel region has a channel width defined along a directionperpendicular to the channel length, and wherein the channel lengths areuniform in a direction of the channel width.
 8. The thin filmsemiconductor device of claim 1, the semiconductor layer beingelongatable, such that when the substrate is elongated in the firstdirection, the channel lengths of the plurality of first portions of thechannel region decrease, and the channel lengths of the plurality ofsecond portions of the channel region increase, the source, drain andchannel regions being designed such that the increases in the channellengths balance out the decreases in the channel lengths, and such thatwhen the substrate is elongated in the second direction, the channellengths of the plurality of second portions of the channel regiondecrease, and the channel lengths of the plurality of first portions ofthe channel region increase, the source, drain and channel regions beingdesigned such that the increases in the channel lengths balance out thedecreases in the channel lengths.
 9. The thin film semiconductor deviceof claim 1, wherein the TFT further comprises a bottom gate electrodedisposed between the substrate and the channel region of thesemiconductor layer and a top gate electrode disposed on the channelregion of the semiconductor layer, wherein when the thin filmsemiconductor device is rolled, folded or subjected to tensile forces,any change in a distance between the top gate electrode and thesemiconductor layer is offset by a commensurate change in distancebetween the bottom gate electrode and the semiconductor layer.
 10. Anorganic light-emitting display device, comprising: a flexibly extendablesubstrate, the substrate being extendable in a first direction and thesubstrate being extendable in a second direction perpendicular to thefirst direction, the flexibly extendable substrate being comprised of aplastic material; a flexibly extendable thin film transistor (TFT)disposed on the substrate and comprising a semiconductor layercomprising a source region, a drain region and a channel region betweenthe source and drain regions, the channel region having a channel lengthbeing a distance between the source region and the drain region at aparticular location on the channel region, the source and drain regionshaving spiral shapes; a bottom electrode electrically connected to theTFT; a top electrode provided on the bottom electrode; and an emissionlayer (EML) disposed between the bottom electrode and the top electrodeand comprising an organic emission layer, wherein the channel regioncomprises a plurality of first portions having channel lengths extendingperpendicular to the first direction and a plurality of second portionshaving channel lengths extending perpendicular to the second direction,wherein an area occupied by the first portions and an area occupied bythe second portions are adjusted so that an average channel length ofthe thin film transistor remains unchanged upon the thin filmsemiconductor device being rolled, folded or subjected to tensileforces.
 11. The organic light-emitting display device of claim 10,wherein a part of the source region is spaced apart from the drainregion and partially surrounds the drain region, and wherein a part ofthe drain region is spaced apart from the source region and partiallysurrounds the source region, the source and drain regions each having ahigher impurity concentration than the channel region.
 12. The organiclight-emitting display device of claim 10, wherein the source region andthe drain region have 180 degree rotational and symmetrical relationshipwith respect to a center point of the semiconductor layer.
 13. A thinfilm semiconductor device, comprising: a flexible elongatable substrateextending in a first direction and a second direction perpendicular tothe first direction, the flexible elongatable substrate being comprisedof a plastic material; a flexible semiconductor layer disposed on theflexible elongatable substrate, comprising first and second surfacesfacing each other, and a channel region; a source electrode and a drainelectrode provided on the first surface or the second surface of thesemiconductor layer and disposed at both sides of the channel regionalong the channel region of the semiconductor layer at locationscorresponding to the source and drain regions respectively of thesemiconductor layer; a first gate electrode provided on the firstsurface of the semiconductor layer, spaced apart from the semiconductorlayer and overlapping with at least a part of the semiconductor layer;and a second gate electrode provided on second surface of thesemiconductor layer, spaced apart from the semiconductor layer andoverlapping with at least a part of the semiconductor layer, wherein thechannel region comprises a channel length defined as a distance betweenthe source region and the drain region, a plurality of first portionshaving channel lengths perpendicular to the first direction, and aplurality of second portions having channel lengths in a directionperpendicular to the second direction, wherein when the thin filmsemiconductor device is rolled, folded or subjected to tensile forces,the source, drain and channel regions of the semiconductor layer aredesigned so that a channel length change within the second portionsoffsets a channel length change within the first portions.
 14. The thinfilm semiconductor device of claim 13, wherein when the flexibleelongatable substrate is elongated in the first direction, the channellengths of the plurality of first portions of the channel regiondecrease, and the channel lengths of the plurality of second portions ofthe channel region increase a corresponding amount, and wherein when theflexible elongatable substrate is elongated in the second direction, thechannel lengths of the plurality of second portions of the channelregion decrease, and the channel lengths of the plurality of firstportions of the channel region increase a corresponding amount so thatthe electrical characteristics of the thin film transistor remainunchanged.
 15. The thin film semiconductor device of claim 13, whereinwhen the flexible elongatable substrate is elongated, a change rate ofsize of the semiconductor layer according to an elongation direction ishigher than that of an average channel length of the channel region. 16.The thin film semiconductor device of claim 13, wherein the sourceregion and the drain region have line shapes each comprising a firstedge closer to a center of the TFT and a second edge farther from thecenter of the TFT, respectively, and each comprising a first portionextending from the first edge, a second portion connected to the firstportion and extending in a direction perpendicular to a direction inwhich the first portion extends, a third portion connected to the secondportion and extending in an opposite to the direction in which the firstportion extends, and a fourth portion connected to the third portion andextending in an opposite to a direction in which the second portionextends, respectively, wherein lengths of the first and third portionsare adjusted so that an average channel length does not change upon thinfilm semiconductor device being rolled, folded or subjected to tensileforces.
 17. The thin film semiconductor device of claim 3, wherein aradius of curvature of the second arc portion being two times a radiusof curvature of the first arc portion.
 18. The thin film semiconductordevice of claim 13, wherein when the thin film semiconductor device isrolled, folded or subjected to tensile forces, any change in a distancebetween the first gate electrode on the first surface and thesemiconductor layer is offset by a commensurate change in distancebetween the second gate electrode on the second surface and thesemiconductor layer.
 19. The thin film semiconductor device of claim 9,wherein the bottom gate electrode and the top gate electrode areelectrically connected to each other and have a same electric potential.20. The thin film semiconductor device of claim 13, wherein the firstgate electrode and the second gate electrode are electrically connectedto each other and have a same electric potential.